Circuit miniaturization allows circuits of many different types to be contained on a single chip. The different circuits that are contained on a chip may have different power requirements. In order to make the most efficient use of available power, power can be managed so that appropriate voltages are allocated to the various circuits. By managing the power appropriately, power consumption of the chip can be reduced. A level shifter circuit can be used between circuit blocks that have different power domains, e.g., use different power sources.
FIG. 1 shows a conventional level shifter circuit 100. In FIG. 1, conventional level shifter 100 bridges respective power supply voltage domains that correspond to supply voltages Vdd1 117 and Vdd2 119. As is shown in FIG. 1, the power supply voltage domains share a common ground (gnd) 121. Complimentary, full-swing signals in the power supply voltage domain corresponding to supply voltage Vdd1 117 are converted into complimentary, full swing signals in the power supply voltage domain corresponding to supply voltage Vdd2 119.
In operation, referring to FIG. 1, when either the voltage at node in 101 or node inb 103 exceeds Vtn relative to gnd 121 an input NFET, either 105 or 107 respectively, turns “on”. When node in 101 goes “high”, node intb 123 falls and drives output terminal out 127 “high”. When node intb 123 falls, cross coupled PFET 111 is turned “on” which drives node int 125 “high”. When node int 125 rises, node outb 129 is driven “low”.
However, level shifter 100 is susceptible to noise and leakage when the input power supply is powered down. When the input power supply Vdd1 117 is powered down (zero volts) circuit input drivers assume a high impedance condition. In conventional designs such as that shown in FIG. 1, both inputs are weakly driven to zero by leakage currents from the input power supply Vdd1 117 and gnd 121. Because the inputs 101 and 103 are weakly driven to zero, they are susceptible to coupled noise injection which they may be very slow to recover from.
Noise on the input terminals 101 and 103 can turn on the NFETs 105 and 107 respectively and can produce unwanted leakage currents from Vdd2 119 and gnd 121 due to crowbar current flowing through the FETs 109 and 105 or FETs 111 and 107. Leakage currents dissipate power. Also, noise on input terminals 101 and 103 can create erroneous outputs at the output terminals 127 and 129. Also shown in FIG. 1 is inverters 113 and 115 and node intb 123.